1. Field of the Invention
The present invention relates to a nonvolatile memory device, for example, an electrically erasable nonvolatile memory device such as a flash EEPROM.
2. Description of the Related Art
A NAND type flash EEPROM, for example, comprises an N-type substrate on which are placed P-wells over which in turn are formed memory cells.
In a NAND type flash EEPROM having such a construction, in an erasing operation, when a high voltage (about 20 V) is applied to a P-well and an N-type substrate, and a control gate are maintained at 0 V, a tunnel-effect current then flows and the electrons are injected to the P-well. As a result, a threshold voltage V.sub.th of the memory cell shifts from positive to negative.
Specifically, in a write operation, the N-type substrate, P-well, and diffusion layer are maintained at 0 V and a high voltage (about 20 V) is applied to the control gate, whereupon a tunnel-effect current flows and electrons are injected into the floating gate. As a result, the threshold voltage V.sub.th of a memory cell shifts from negative to positive.
Explaining this more specifically using a cell array, when writing the data "0", a bit line of the memory is set to 0 V, while when writing the data "1", the bit line is set to 7 V. A voltage of 20 V is applied to the control gate of the selected memory transistor, while 10 V is applied to other control gates of the other non-selected memory transistors.
When the bit line is set to 0 V, a potential difference of 20 V is given between a channel and the control gate, tunnel-effect electrons are injected into the floating gate, and the threshold voltage V.sub.th of the memory cell shifts from negative to positive. On the other hand, when a bit line is set to 7 V, the potential difference between the channel and the control gate becomes 13 V and so the threshold voltage V.sub.th is held at the negative level as at the time of the erasing operation.
In a read operation, 5 V is applied to the bit line and 0 V to the source line, and 0 V is given to the control gate of the selected memory cell and 5 V to other control gates of the non-selected memory cells.
The non-selected memory cells must be kept in the ON state regardless of the data. Therefore, the threshold voltage V.sub.th of these memory cells is controlled to a predetermined value, for example, not more than 3.5 V.
By applying 0 V to the control gate of the selected memory cell, the threshold voltage V.sub.th is negative when the data is "1", so the cell becomes the ON state (depletion state) and a cell current flows.
On the other hand, when the data is "0", the threshold voltage V.sub.th is positive, so the cell becomes the OFF state (enhancement state) and no cell current flows. As a result, whether the data is the "1" or "0" determines if a cell current flows from the bit line to the source line through a plurality of cells.
In a NAND type EEPROM, as explained above, when the write data is "0", the threshold voltage V.sub.th must be positive. More specifically, the condition 0.5 V&lt;V.sub.th must be satisfied, so in a write operation, a check is made to see if a sufficient write operation was performed and the threshold voltage V.sub.th shifted to the level corresponding to the write data.
One method used for such a check has been, for example, a bit verification method for checking each bit.
FIG. 1 is a circuit diagram of a NAND type flash memory using the bit verification method.
In FIG. 1, S/A denotes a sense amplifier, EQL an equalizing circuit, VRFa and VRFb verification circuits, (a) and (b) cell arrays, CDC a column decoder, BLa and BLb bit lines, SEL0a, SEL1a, SEL0b, SEL1b selection gate lines, and WL0a to WL3a, WL0b to WL3b word lines.
The sense amplifier S/A is of the latch type of an open bit line form and is comprised of PMOS transistors PT1, PT2, and PT12 and NMOS transistors NT1, NT2, NT12.
The drains and gates of the PMOS transistor PT1 and the NMOS transistor NT1 and the drains and gates of the PMOS transistor PT2 and NMOS transistor NT2 are connected with each other, a connection point between the PMOS transistor PT1 and NMOS transistor NT1 (first node) and a connection point between the PMOS transistor PT2 and NMOS transistor NT2 are connected, a connection point between the PMOS transistor PT1 and the NMOS transistor NT1 and a connection point between the drains of the PMOS transistor PT2 and the NMOS transistor NT2 (second node) are connected, thereby forming a CMOS flip-flop.
Further, the sources of the PMOS transistors PT1 and PT2 and the sources of the NMOS transistors NT1 and NT2 are connected, a connection point between the sources of the PMOS transistors PT1 and PT2 is connected through the PMOS transistor PT12 to the supply source of the voltage V.sub.SAH, and a connection point between the sources of the NMOS transistors NT1 and NT2 is connected through the NMOS transistor NT12 to a power source of the voltage V.sub.SAL.
A connection point between the drains of the PMOS transistor PT1 and the NMOS transistor NT1, that is, a first node, is connected through a verification circuit VRFa to the bit line BLa. A point of connection between the drains of the PMOS transistor PT2 and the NMOS transistor NT2, that is, the second node, is connected through the verification circuit VRFb to the bit line BLb.
Further, a connection point between the drains of the PMOS transistor PT1 and the NMOS transistor NT1 and a connection point between the drains of the PMOS transistor PT2 and the NMOS transistor NT2 are connected through the NMOS transistors NT5 and NT6 to a not shown main data line.
Note that the gate voltages of the NMOS transistors NT5 and NT6 are controlled by the column decoder CDC.
The equalizing circuit EQL is comprised of serially connected NMOS transistors NT3 and NT4 and is connected in parallel with respect to the sense amplifier S/A, that is, between a connection point between the drains of the PMOS transistor PT1 and NMOS transistor NT1 and a connection point between the drains of the PMOS transistor PT2 and the NMOS transistor NT2. The gates of the NMOS transistors NT3 and NT4 are connected to a supply line of the equalizing signal Ve, while a connection point between the NMOS transistors NT3 and NT4 is connected to the power feeding line of a power supply of (1/2) V.sub.cc.
The verification circuit VRFa is comprised of the NMOS transistors NT7a to NT9a and converts data at the time of the verification operation.
The NMOS transistor NT7a is connected between a connection point between the drains of the PMOS transistor PT1 and NMOS transistor NT1 of the sense amplifier S/A and the bit line BLa, while the NMOS transistors NT8a and NT9a are connected in series between the bit line BLa and the power supply V.sub.cc.
The gate of the NMOS transistor NT7a is connected to a supply line of the signal Vta, while the gate of the NMOS transistor NT8a is connected to a connection point between the drains of the PMOS transistor PT1 and NMOS transistor NT1 of the sense amplifier S/A, that is, the first node. The gate of the NMOS transistor NT9a is connected to a signal line of the signal Vav.
The verification circuit VRFb is comprised of the NMOS transistors NT7b to NT9b and converts data at the time of a verification operation.
The NMOS transistor NT7b is connected between a connection point between the drains of the PMOS transistor PT2 and NMOS transistor NT2 of the sense amplifier S/A and the bit line BLb, while the NMOS transistors NT8b and NT9b are connected in series between the bit line BLb and the power supply V.sub.cc.
The gate of the NMOS transistor NT7b is connected to the supply line of the signal Vtb, while the gate of the NMOS transistor NT8b is connected to a connection point between the drains of the PMOS transistor PT2 and NMOS transistor NT2 of the sense amplifier S/A, that is, the second node. The gate of the NMOS transistor NT9b is connected to a signal line of the signal Vbv.
The cell array (a) is comprised of selection gates SG0a and SG1a comprised in turn of the memory transistors MT0a to MT3a.
The memory transistors MT0a to MT3a are connected in series. Their gates are connected to the word lines WL0a to WL3a.
The drain of the memory transistor MT0a is connected through the selection gate SG0a to the bit line BLa, while the source of the memory transistor MT3a is connected through the selection gate SG1a to the ground.
The gate of the selection gate SG0a is connected to the selection gate line SEL0a, while the gate of the selection gate SG1a is connected to the selection gate line SEL1a.
Further, the bit line BLa is connected through a precharge transistor PRa comprised of an NMOS transistor to the signal line of the voltage Va, while the gate of the transistor PRa is connected to the signal line of the precharge signal Vpa.
The cell array (b) is comprised of the selection gates SG0b and SG1b comprised in turn of the memory transistors MT0b to MT3b, a dummy memory cell DMC, and an NMOS transistor.
The memory transistors MT0b to MT3b and the dummy memory cell DMC are connected in series. Their gates are connected to the word lines WL0b to WL3b and DWL, respectively.
The drain of the memory transistor MT0b is connected through the selection gate SG0b to the bit line BLb, while the source of the dummy memory cell DMC is connected through the selection gate SG1b to the ground.
The gate of the selection gate SG0b is connected to the selection gate line SEL0b, while the gate of the selection gate SG1b is connected to the selection gate line SEL1b.
Further, the bit line BLb is connected through a precharge transistor PRb comprised of an NMOS transistor to the signal line of the voltage Vb, while the gate of the transistor PRb is connected to the signal line of the precharge signal Vpb.
Here, an explanation will be given of the verification operation in the above configuration based on the timing chart of FIG. 2 using the cell array (a) as the reading side and the cell array (b) as the reference side.
First, before the verification operation, the immediately previous write data is latched in the sense amplifier S/A. Further, the dummy cell DMC on the reference side at the time of a read operation is in a state erased by ultraviolet light with no cell current flowing through it.
In such a state, first, the precharge signals Vpa and Vpb are set to the high level in the interval between the period t1 and t2 and are supplied to the gates of the precharge transistors PRa and PRb. As a result, the read side bit line BLa is precharged to the voltage of Va and the reference side bit line BLb is precharged to the voltage of Vb. In actuality, for example, the read side bit line BLa is precharged to a voltage higher than that of the reference side bit line BLb. That is, the voltages Va and Vb are set so that V.sub.cc &gt;Va&gt;Vb.
Next, the voltages of the word lines WL and the selection gate lines SEL are set to the high level in the interval of the periods t2 to t3.
At this time, if cell current is flowing, the data of the selected cell is "1" and the voltage of the read side bit line BLa falls below the voltage of the reference side bit line BLb.
As opposed to this, if no cell current is flowing, the data of the selected cell is "0" and the voltage of the read side bit line BLa is higher than the voltage of the reference side bit line BLb.
Next, after the voltage of the word line WL drops, an activation signal Vav is set to the high level in the interval between the times t3 to t4 and is supplied to the gate of the NMOS transistor NT9a of the verification circuit VRFa.
At this point of time, since the write data is latched in the sense amplifier S/A, for example, if after the data "1" has been written, the NMOS transistor NT8a of the verification circuit VRFa becomes ON.
As a result, the read side bit line BLa is recharged past the voltage of the reference side bit line BLb up close to the V.sub.cc level regardless of the read cell data.
Next, the signal Vp is set to the high level and the signal Vn to the low level, the transistors PT12 and NT12 of the sense amplifier S/A are placed in the OFF state, the equalizing signal Ve is set to the high level, and the same is supplied to the gates of the transistors NT3 and NT4 of the equalizing circuit EQL. By this, the CMOS flip-flop of the sense amplifier S/A is equalized, so the amplifier operates as a so-called differential amplifier.
Next, the signals Vta and Vtb are set to the high level and are supplied to the gates of the transistor NT7a of the verification circuit VRFa and the transistor NT7b of the verification circuit VRFb.
As a result, the transistors NT7a and NT7b enter the ON state, a sense operation is performed, and the sensed verification read data is latched in the sense amplifier S/A and used as the rewrite data.
In this way, the data conversion required for verifying each bit is performed.
More specifically, when the write data is "0" and the cell data is "0", the rewrite data is "1", when the write data is "0" and the cell data is "1" the rewrite data is "0", when the write data is "1" and the cell data is "0" the rewrite data is "1" and when the write data is "1" and the cell data is "1", the rewrite data is "1".
However, in the above-mentioned circuit, as shown in FIG. 2, after the word line voltage rises and falls in the interval of the periods t2 to t3 and data is read out, data conversion is performed by raising the activation signal Vav in the interval between the periods t3 and t4, so the sense operation is delayed and time is taken for the verification operation. As a result, there is the problem of unsuitability for a high speed read operation.